module lzd_28bit #(
    parameter WIDTH = 28
) (
    input [WIDTH-1:0] data,
    output reg [5:0] count
);
    always @(*) begin
        casez (data)
            // 修正每个case项的模式，确保前导零数目与count对应
            28'b1??????????????????????????? : count = 0;
            28'b01?????????????????????????? : count = 1;
            28'b001????????????????????????? : count = 2;
            28'b0001???????????????????????? : count = 3;
            28'b00001??????????????????????? : count = 4;
            28'b000001?????????????????????? : count = 5;
            28'b0000001????????????????????? : count = 6;
            28'b00000001???????????????????? : count = 7;
            28'b000000001??????????????????? : count = 8;
            28'b0000000001?????????????????? : count = 9;
            28'b00000000001????????????????? : count = 10;
            28'b000000000001???????????????? : count = 11;
            28'b0000000000001??????????????? : count = 12;
            28'b00000000000001?????????????? : count = 13;
            28'b000000000000001????????????? : count = 14;
            28'b0000000000000001???????????? : count = 15;
            28'b00000000000000001??????????? : count = 16;
            28'b000000000000000001?????????? : count = 17;
            28'b0000000000000000001????????? : count = 18;
            28'b00000000000000000001???????? : count = 19;
            28'b000000000000000000001??????? : count = 20;
            28'b0000000000000000000001?????? : count = 21;
            28'b00000000000000000000001????? : count = 22;
            28'b000000000000000000000001???? : count = 23;
            28'b0000000000000000000000001??? : count = 24;
            28'b00000000000000000000000001?? : count = 25;
            28'b000000000000000000000000001? : count = 26;
            28'b0000000000000000000000000001 : count = 27;
            28'b0000000000000000000000000000 : count = 28;  // 处理全零情况
            default: count = 0; // 此default理论上不会触发
        endcase
    end
endmodule